Syllabus - ECE course 361-1-4201 & 381-1-0107

Introduction and fundamental concepts, ISA and MIPS, MIPS architecture, Single-cycle and Multi-cycle CPU, Pipeline architecture, Memory Hierarchy, Exceptions, Caches, Parallelization (instruction level, data level and multi-threading).

Schedule - Spring semester 2020

On mobile devices swipe the table right-left
Meeting Date Topic Material Lab/Assignment
8/3/20 Beginning of Semester
12/3/20 No class due to Covid19 issues :-(
1 19/3/20 Onlie teaching! Introduction - Course Overview and requirements.
Basics and Fundamental Concepts
Course Administration
Introdction and Basics 1
Introdction and Basics 2
Fundamental Concepts
2 26/3/20 ISA and MIPS ISA tradeoffs
ISA tradeoffs and MIPS ISA
Lab1: VHDL part1.
Task #1 publication
3 2/4/20 MIPS Architecture ISA tradeoffs (cont.) and MIPS ISA
MIPS Architecture - Chapter 6 from H&H
Home assignment #1
no class 9/4/20 and 16/4/20 Passover vacation
4 23/4/20 Microarchitecture Single cycle microarchitecture
Multi-cycle microarchitecture
Microarchitecture - Chapter 7 from H&H
Lab2: VHDL part 2.
Task #1 submission
Task #2 publication
5 30/4/20 Pipeline Mapping control to hardware (CO&D 5th Ed., Appendix D)
Pipelining I
Pipelining II
6 7/5/20 Branch and Prediction Branch and Prediction I Home assignment #2
Lab3: FPGA, Quartus
7 14/5/20 Branch and Prediction (cont.) Branch and Prediction II
8 21/5/20 Exception and Maintenance states. OoO. Exceptions State, Maintenance State and Recovery
Out of Order Execution
Lab4: Task 2 demonstration.
Task 2 submission.
Task 3 publication.
no class 28/5/20
9 4/6/20 GPU, VLIW, DAE, Memory Hierarchy, Caches GPU, VLIW, DAE
Memory Hierarchy
Memory Hierarchy Design
Lab5: MIPS architecture.
10 11/6/20 Caches Caches I
Caches II
11 18/6/20 Parallelism I
Instruction-level Parallelism.
Data-level Parallelism.
Instruction-Level Parallelism
Data-Level Parallelism
Home assignment #3.
Lab 7 CE only. Project preparation.
CE only - Final projects publication.
12 25/6/20 Parallelism II
Thread-level Parallelism.
Thread-Level Parallelism
Multiprocessors
Historical Perspectives
Lab6: Task 3 demonstration.
13 Buffer xx/6/20
26/6/20 End of Semester
xx/xx/20 Final exam, term A
xx/xx/20 Final exam, term B Lab8 CE only: Final projects demonstrations.

Grades

Electrical and Computer Engineering (EE/361):


3 home assignments - 1% each. Overall 3%
3 lab assignments - #1 4%, #2 8%, #3 12%. Overall 24%
4 lab experiments - 1.5% each, Overall 6%
Final exam: 67%

Computer Engineering (CE/381):


3 home assignments - 1% each. Overall 3%
3 lab assignments - #1 4%, #2 8%, #3 12%. Overall 24%
4 lab experiments - 1.5% each, Overall 6%
Final project: 15%
Final exam: 52%

References

Recommended text books:
1) John Hennessy and David Patterson - Computer Architecture.
5th Edition (MIPS for the present course).
Computer Architecture

6th Edition (RISC-V in the near future...).
Computer Architecture

2) David Money Harris and Sarah L. Harris, "Digital Design and Computer Architecture", second edition
Digital Design and Computer Architecture


This course is heavily based on "18-447 Introduction to Computer Architecture – Spring 2015" by Prof. Onur Mutlu from Carnegie Mellon University.
Slides and videos are available here. The videos are also available on Youtube.
Another excellent reference is ELE475 from Princeton University by Prof. David Wentzlaff
This course is also available on Coursera.

Reading materials (papers) and home assignments are published at the course Moodle.

About

Where: Hall 1, Building 35.
When: Thursdays, 6pm-9pm.
Reception hour: immediately after class.
Lecturer: Dr. Guy Tel-Zur.
Contact: guycomputing @ gmail . com